The semiconductor industry has had tremendous success in delivering ever more cost effective chips to market through the use of scaling. However, while scaling works well in device or front-end semiconductor processing, device wiring is not amenable to scaling and results in degraded interconnect resistance and/or capacitance. To alleviate this problem, the industry has been migrating to the use of a lower resistance conductor, such as copper (Cu), and is also introducing lower-k insulators (k=dielectric constant) to reduce capacitance in damascene interconnect and/or device structures. Newly developed insulators in the ultra-low-k (ULK) range (k<2.5) are generally characterized by a great deal of porosity (e.g., 30-50%). These materials are extremely fragile and difficult to integrate since they are susceptible to contamination from other sources.
In a dual-damascene (DD) structure, a single metal deposition step is used to simultaneously form Cu metal lines and vias. The Cu metal lines and vias are formed by filling recessed features, such as a trench, a via, or other interconnect structure, in a dielectric film or substrate. After filling, the excess Cu metal that is deposited outside the recessed feature is removed by a chemical-mechanical polishing (CMP) process, thereby forming a planar structure with metal interconnect inlays.
An interface exposed by Cu CMP, and subsequently capped by a dielectric layer, such as low-k or ULK insulators, is critical to the performance and reliability of copper interconnects on semiconductor devices. An interaction between the dielectric capping layer and the underlying copper often limits an electromigration reliability of the interconnect. The ability of this dielectric layer to serve as a barrier to copper diffusion and the cleanliness of the interface (especially presence of trace amounts of copper) between the dielectric capping layer and underlying dielectric layer in the interstices between copper lines can limit a dielectric breakdown reliability and line-to-line leakage performance of the interconnect.